報告題目🍤♎️：When Deep Learning Meets IC Fabrication: A Data-Driven Approach to IC Design for Manufacturability
報告人♞：林嘉文 教授
報告時間🚛：07月10日 15:00
報告地點：912會議室
報告人簡介:
林嘉文教授於2000年獲臺灣清華大學（NTHU）電機工程專業博士學位，現為臺灣清華大學電機系教授，IEEE Fellow，2018 - 2019年IEEE電路與系統學會的傑出講師。研究領域包括圖像/視頻處理和視頻網絡🧟。現任NTHU人工智能研究中心副主任，NTHU EECS恒达多媒體技術研究中心主任🧑🏻🍳，中國圖像處理與模式識別協會臺灣地區會長。曾擔任Associate Editor of IEEE Transactions on Image Processing, IEEE Transactions on Multimedia, IEEE Transactions on Circuits and Systems for Video Technology, IEEE Multimedia期刊副編輯。還擔任了2013-2015年度IEEE Transactions on Multimedia指導委員會成員🏃🏻♀️➡️，及IEEE CASS多媒體系統和應用技術委員會主席；於2010年擔任IEEE ICME技術計劃聯合主席並於2019年擔任臺北IEEE ICIP的TPC主席。他的論文榮獲IEEE VCIP 2015最佳論文獎及SPIE VCIP 2005年度青年研究者獎🏅。
報告內容簡介:
Traditionally, after ID circuit design and layout, it takes months to fabricate an IC wafer, involving a multiple-step sequence of photolithographic and chemical processing, which can significantly deform the layout patterns and is too complex to model mathematically. Usually we cannot identify defects (e.g., broken wires) of metal wires due to deformations of layout patterns caused by IC fabrication until capturing the scanning electron microscope (SEM) images of fabricated IC wafers, making the circuit design and verification very costly and time-consuming. To address the above problem, there two essential concerns in terms of IC design for manufacturability: (1) How to predict the manufactured IC circuitry from an IC layout so as to assess the layout quality accordingly in a pre-simulation process, and (2) How to automatically modify IC layout patterns so that the manufactured IC circuitry can match the desired patterns as possible. In this talk, we will show how deep-learning-based image prediction can assist IC design for manufacturability. To this end, we formulate the lithography and etching processes of metal layers as a set of nonlinear warping functions between a patch of IC layout pattern and its corresponding SEM image, and models the set of warping functions using a CNN-based LithoNet parametrized with IC fabrication parameters. Based on LithoNet, we also propose a CNN-based OPCNet that can automatically modify an IC layout pattern so that its fabricated IC circuitry well match the desired layout pattern, the so-called Optical Proximity Correction (OPC) process.
